1. Field of the Invention
The present invention generally relates to digital data transmission in a communication network and more specifically relates to mechanisms for performing a boundary scan or roving link test on a wired or wireless network.
2. Related Art
Today's networks are very error-prone and difficult to deploy, diagnose and repair. When a network fails, it is difficult and labor intensive to locate the trouble spots. For example, in a system where routing tables are used, the information in the routing table is no longer valid when a failure has occurred. An internet control message protocol (“ICMP”) or similar type of protocol can be used to report errors, locate certain faults and monitor network performance. A significant drawback in self-organizing wired or wireless packet networks, however, is the inability to test all possible alternate routes, i.e., routes that are not currently in use but may be required when existing routes have unsatisfactory signal transmission or total failure.
Boundary scan support devices allow the IEEE 1149.1 standard joint test action group (“JTAG”) to be used as a backplane bus which opens up possibilities of backplane interconnect test and multi-drop architectures, enabling backplane-to-board-to-chip diagnostics in system integration and field service scenarios. For example, all the memory components of an IC chip can be connected in a long shift register, at minimal overhead, and then a general-purpose serial port on the chip is used to shift arbitrary test vectors into and out of the chip. These test vectors allow the whole chip to be exercised and the results compared to a working chip to verify correctness. All complex chips today are tested via JTAG capable interfaces, and the technology is also used to implement hardware debugging of microprocessors.
In addition, development of the IEEE 1532-2000 in-system configuration standard leverages IEEE 1149.1 structures to enable programming of complex programmable logic devices (“CPLDs”) and field programmable gate arrays (“FPGAs”) in situ. Today the IEEE 1149.1 standard is limited to digital electronics, and commonly covers only chips with JTAG capabilities. Nevertheless, in a few years, the IEEE 1149.4 standard for a Mixed-Signal Test Bus, will make testing of analog circuitry possible as well.
Graph theory is an area of mathematics that deals with entities (called nodes) and the connections (called links) between the nodes. An important traversal problem is to find a tour in a given graph that traverses each edge exactly once and end up at the originating node. Such a tour is called an Euler tour. An Euler tour is possible only if every node has an even number of links attached to it. This is called having an even degree.
Since an Euler tour does not exist in all graphs, a common problem is to determine a minimum length tour that traverses each link at least once. This problem is known as the postman problem. A process called graph Eulerization is used to add duplicate links to the graph. These duplicate links are added in such a fashion that they provide each node in the graph with an even number of attached links. A generalization of the postman problem, known as the rural postman problem, is to determine a least cost traversal of a specified subset of links in the graph. A rural postman tour of an undirected or directed graph can be computed in polynomial time, whereas a rural postman tour of a mixed graph (i.e., a graph having undirected and directed links) is NP-hard. A simple solution is to replace all sub-graphs of even degree with edges indicating a traversal cost, and then compute a minimum matching on the vertices of odd degree.
In recent years network protocol conformance tests have been created that use the rural postman tour algorithm. In this technique, two deterministic finite state machines are used to model the protocol specification and the protocol implementation, respectively. The test is thus to compare the results of the traversal by the two state machines, with a focus of minimizing the total test sequence length. A postman tour technique can similarly be used for traversing all of the links of a network based on the network routing tables. However, the time varying signal transmission and reception conditions in a network often make a statically constructed rural postman tour incomplete at run time. Therefore, the industry lacks a robust way to test the link status of a wired or wireless network in real time a need has been created for a solution that has yet to be filled.